Interface Masters Smart Switch Delivers 11.2tbps Switching and Routing With Xsight Labs DPUs
Xsight Labs, represented by VP of BizDev Ted Weatherford and distinguished engineer John Carney, introduced a smart switch developed with Interface Masters, designed for government security applications. This 1RU device offers 28x 400G connectivity using modern QSFP112 100G SerDes, powered by Xsight Labs’ X2 12.8terabit Ethernet switch chip. A key feature is 1.6 terabits of line-rate stateful processing (Layer 4-7) provided by two E1 DPUs, which together offer 128 ARM cores and up to 1 terabyte of DRAM (0.5 TB per DPU). This solution boasts significantly higher compute and networking density per rack unit compared to incumbent offerings, delivering a “line rate smart switch” that is available bare metal.
The presentation also showcased a larger 6.4 terabit top-of-rack (ToR) solution, integrating eight E1 DPU add-in cards into a PCIe motherboard, providing 500 Neoverse 2 ARM cores and up to 2 terabytes of memory. This proof of concept, developed for a major US Cloud Service Provider, demonstrated substantial power and cost savings, up to 25% less power and less than half the cost, compared to traditional deployments. Crucially, both the E1 and X2 chips incorporate comprehensive packet timing features, including a stratum three clock, real-time clock logic for timestamping interfaces, PTP synchronization, and physical PPS in/out connectors, making them suitable for timing-sensitive applications.
Xsight Labs positions its X-series Ethernet switch as a superior ToR upgrade strategy for AI and general compute fabrics. Instead of relying on expensive, high-power, and often oversized 51.2 terabit switches, their solution offers a programmable, high-performance alternative at a fraction of the cost ($1,500 vs. $14,000), consuming significantly less power (300-400 watts) and occupying just one RU. This not only frees up rack space for additional GPUs but also provides lower latency and flexible congestion management. By optimizing for typical ToR needs, where downlink speeds rarely exceed 400 gig per NIC, Xsight Labs aims to reduce overall infrastructure costs and power consumption in data centers and infrastructure-as-a-service environments.
Presented by Ted Weatherford, Vice President of Business Development, Xsight Labs, and John Carney, Distinguished Engineer, Software Architecture, Xsight Labs. Recorded live at AI Infrastructure Field Day in Santa Clara on January 29th, 2026. Watch the entire presentation at https://techfieldday.com/appearance/xsight-labs-presents-at-ai-infrastructure-field-day/ or visit https://techfieldday.com/event/aiifd4/ or https://xsightlabs.com/ for more information.
Transcript
I'm Ted Weatherford. I'm VP of Biz Dev at XXI Labs. Joined with me is distinguished engineering architect John Kari.
Nice to meet here. Thanks man. Uh, smart Switch is an application, um, where you are going to have usually an ethernet switch and you're gonna have some stateful processing and I'll, I'll cover a product that we're doing with a company local in San Jose area called Interface Masters.
Uh, interface Masters is helping us with security type applications for governments. So it's an all American hardware, Taiwanese chips, Israeli design, American design box. Um, and it offers a one RU with 28 by 400 gig connectivity.
And it's four oh gig connectivity with a hundred gig ser called A-Q-S-F-P one 12. That's new and modern and efficient. That's why you might do it.
8 terabit ethernet switch chip. It has 120 800 gig 30 on it and most of the s go out the front panel and give you that 400 gig connectivity. So you can tap into your network with a lot of bandwidth, but there's two E ones and each E one is capable of 800 gig line rate.
6 terabit, a pool of what we call layer four to layer seven or stateful processing, do whatever you want with a packet. You also have a large number of arm cores. It gives you 128 total arm cores in a one ru and it gives you the max dram from those two, uh, E one DPS two, which would be, how much John is that?
The eight banks of DRAM would, that'd be like 128 gigabyte or 256 gigabyte. I can't remember. So the maximum we can support on an E one is, is a half a terabyte of of dram.
Yeah, that's what I wish I was coming up with really quick. Um, okay. So these are offered by companies like Cisco, but you won't find this kind of compute density.
They'll typically take eight 200 gig duss that really run about a hundred gig of processing. Um, and they'll need, you know, two, two rack units to do about a quarter of this bandwidth best case. So we are just offering an a ridiculous amount of compute density and networking density per iu, uh, compared to, uh, what, uh, what others do.
And this is available bare metal meaning without any software on it. Um, so that if somebody wanted to run with this form factor quick, we can take this design to Taiwan, like a hyperscaler might want to or we can sell them right here in, in in River City. So we're really excited about this because in my lifetime we all wanted smart switches.
We want, we want a line rate smart switch is what we really want. 6 terabit. 4 T designed a big chunk in server looking thing that's gonna sit anywhere you want 'cause it's ethernet connected, but typically at the top of a rack or maybe even in your leaf.
4 terabyte of connectivity, okay. 4 terabyte of processing. So now you've got eight of our cards.
This is an a IC card as one of our E one chips on it. And inside that ugly black box, there's eight of these plugged into A-P-C-I-U motherboard that just supplies power. And then two by 400 comes out and wraps up to left and right.
2 there. So it's really, you could think of there being eight of these connected to an ethernet switch and then half of the ethernet switch going out to the outside world. 4 T and that's 500 neo verse two arm cores and four times what we said, uh, maybe two terabyte of memory.
So it's pretty cool. And this was done as a proof of concept for a large, a large CSP in the United States, um, to show them that the way they're doing it now, um, conceive them a quarter of the power in less than half the cost. Yeah.
Cool. Ted, quick question. Yeah, maybe a, maybe a basic question, and I'm making any assumptions here as I say it, but time Yeah.
From clocking your board to clocking the nicks to clocking your compute, right? I assume you're gonna be able to ingest any one PPS clock or anything from a fabric perspective or PTP. I'm glad you brought that up because I didn't tout that on here.
And I should have, uh, this product has the packet timing module and like a Okay. Stratum three clock I think. Yeah, yeah.
That's this company interface Masters sells this box with two partners, one's called Red Fig, uh, and one's called Niagara Networks. Uh, and I believe it's Niagara that has all the packet timing. They've got video customers, they got government customers.
Um, yeah, so this actual box does come with the timing. It Does and, and the chips, both of the chips, the E one and the X two have, um, have real time clock, um, uh, logic in there to be able to distribute time throughout the chip so all of the interfaces can timestamp, uh, on those chips. And also, uh, to be able to, you know, filter like the sync packets from PTP and be able to send those to the servo algorithms to be able to sync to the, to the network.
So we have the time, the time synchronization support built into both of the chips. Is there, is there a time GPIO connector on it as well right now? Have you gone that far in that design?
So Physical connector, so The board in a minute. Yeah, so on the adding card you'll see that we actually have like, uh, these very mic microscopic like, uh, coaxial connectors. Um, and on this particular board, uh, we have both a PPS and, and a PPS out.
Okay, got it. Um, and you could, you could potentially daisy chain, you know, multiple of those. Let's pass that one around too.
There's more adding card. That's the highest volume thing we'll probably ship in our company. Uh, 'cause that's your smart nick that would, you know, go into a virtualized host at a infrastructure as a service company right there at 800 or two by four.
Um, yeah, let's, let's, uh, I, I've got a, an application that's, that's really was the impetus of the switch line, the X-er, and I want to close with that because this is the hardest socket in the world to win, probably. Uh, and oh, a a quick question About this. Yeah, sure.
Since, uh, since we were talking about putting eight of these in a box, you, you actually have the PCIE bandwidth to handle Yeah. Come On up on the, the various forts We do. Yeah.
So for the, for the smart switch kind of application, it's all ethernet attached. The actual data planes not running through the, through the PCIE, it's, it's just all net network attached compute. Okay.
Yeah, it's a perfect question 'cause I was on the virtualized host or the air gap, the spartic for infrastructure as a service. And in that application you have the 400 gig connectivity, but when you're running to the host, you've got, you've got full duplex 400 on that with minimum packet, not, not eight. Yeah.
But the bump in the wire application would set kind of where all this started. It's, it's a 800 in and out. Yeah.
Okay. Yeah, no, great. It's like good timing actually for that question.
Um, so that was the E-Series. This is the x-er, the ethernet switch. And what I'm showing here is a standard clo, some people say cloth fabric, Charles CLO fabric.
Um, there's eight planes. Uh, I have plane. One of n well n could be typically eight, it might be two, it might be four.
It's rarely six and it's sometimes eight. And then that's gonna be pizza boxes represented by, uh, the red rectangles. And then below it, each one of those planes will have their own connections.
In this case, two four oh gig connections per plane. So you can have up to 16 by 400 coming into that top rack, which you might want for ai. Um, and this is all front end.
This is all front end scale out connectivity. And then what would you have at the top rack? Well, you would traditionally have the same exact pizza box as you had for your fabric.
8. 2 T switch. We realized that instead of having a switch that costs $14,000, we could make one for $1,500.
We realized that we could build a product that's three or 400 watts barely needing any fans. We can only occupy one R ru. We could make it fully programmable with half of the latency of the incumbent.
And so that was our whole tour upgrade strategy. Um, and I'm just showing a row or a pod where the end rack, I've put our switch in and it would free up one more slot for GPUs at this case. Two, uh, two extra GPUs per rack.
Uh, and it would be a dramatically lower price, lower cost, and it's flexible. So any congestion management scheme, you wanna roll into the switch, you could. And then what's inside the server, hopefully one of these a IC cards.
So again, book ending the tour with programmability, but performance and power that's lower or better than the incumbent. And just saving, saving metal in silicon though. 2 T switches are traditionally a thousand watts and they're two RU and you don't need it.
You need the a hundred giger, you need the 400 gig up but down. You just don't, you don't need it. You're not running a nick faster than 400 gig.
Um, most of 'em are 200. And with that, um, we've really appreciated the chance to, to present to you guys in, in all the interaction.